1. Field
This disclosure relates generally to design and construction of phase locked loop circuits. More particularly, this disclosure relates to the design and construction of phase locked loop circuits that optimize spurious harmonic frequencies usually caused by non-idealities within the components of the phase locked loop circuits.
2. Description of Related Art
Phase locked loops are used for a variety of clocking and synchronizing purposes as is known to those skilled in the art. In all cases, a compromise must be found between the speed in which phase lock is acquired (settling time) and the spectral purity of the output signal. As an example, a phase locked loop is used for frequency synthesis of a local oscillator signal in a receiver to synchronize the receiver with the incoming signal.
FIG. 1 is a block diagram of phase locked loop of the prior art. Referring to FIG. 1, a phase-locked loop 5 has a stable reference oscillator 10 that provides the incoming reference signal FIN that is compared with the output signal FOUT. The output FIN of the reference oscillator 10 is an input to a phase detector 15. The phase detector circuit 15 determines the phase error between the incoming reference signal FIN and the output signal FOUT and provides an output phase error voltage. The phase error is converted into a correction signal that is transferred to the loop filter 20. The loop filter 20 generates a control signal that varies the frequency of the adjustable frequency oscillator 25. The output of the adjustable frequency oscillator 25 is the output signal FOUT. The output signal FOUT is fed to the optional feedback divider 35. The feedback divider 35 divides the output signal FOUT by a factor N to create the feedback signal 40 that is compared in the phase detector 15 to generate the correction signal. When the phase error has been reduced to zero, the adjustable frequency oscillator 25 is not varied and the phase-locked loop 5 is considered locked.
Current practice is to use the so-called type II phase locked loop architecture. This means that two integrators are present inside the loop, which causes the phase error signal to be controlled to be zero in steady state for input phase signals representing a step or a ramp. This phase error signal is usually represented by a pulse width modulated (PWM) square wave signal at the reference frequency. Any residual phase error will cause the tuning signal of the adjustable frequency oscillator to be modulated by a filtered representation of this pulse width modulated signal, visible as spurious components in the output spectrum at offset frequencies that are positive and negative multiples of the reference frequency. In steady state, the pulse width will be zero (or very near zero) and the control signal will have very limited energy at the harmonics of the reference frequency.
A type II PLL is very effective in suppression of the spurious components that are commonly referred to as reference spurs. The reference spurs are eliminated at their source (i.e. the steady state phase error) thanks to the two integrators in the loop. Unfortunately, this brings the control system on the brink of instability and the common remedy is to introduce a zero in the loop transfer function at an appropriate frequency such that the phase margin is sufficient for stable operation. This zero is also present in the closed loop transfer function, which causes overshoot in the step response. This has adverse effects on the settling time.
An application for a phase locked loop is as a frequency synthesizer within the transmitter/receiver for a Digital Enhanced Cordless Telecommunications (DECT) device. DECT is a digital communication standard that is primarily used in cordless telephone systems. DECT is used primarily in home and small office systems, but is also available in many PBX systems for medium and large businesses. DECT can also be used for purposes other than cordless phones such as baby monitors, remote controls for industrial applications. The DECT cordless telephone protocol uses a time division duplex (TDD), time division multiple access (TDMA), and/or a frequency division multiple access (FDMA) protocol. The system choices that were made at its inception have made it very difficult to use all the available time slots and all ten of the available frequencies. A fixed part splits up its time to transmit one time and receive one time per 10 ms to/from one or more portable transmitter/receiver devices. The 10 ms (representing 11,520 data symbol times) frame is divided in 24 slots (12 for transmit and 12 for receive). In principle, a single fixed transmitter/receiver device can be connected to 12 portable transmitter/receiver devices simultaneously. Each of the 480 symbol slots is divided into a payload of 424 symbols and a guard space of 56 symbols (roughly 48.6 μs). This guard space was meant to separate the transmissions of separate portable transmitter/receiver devices in time sufficiently to not interfere with each other. But it is generally too short for the synthesizer in the fixed transmitter/receiver device to tune to a new frequency. Originally the idea was that the fixed transmitter/receiver device would use one or more slots of blind spots to perform that tuning cycle. If the synthesizer cannot tune in less than 465 μs, two active slots must be sacrificed. However, if the synthesizer can be tuned in less than 465 μs, one of the active slots is now sacrificed. But that means that only the even or the odd slots can be used, reducing the number of portable transmitter/receiver devices that can connect to a single fixed transmitter/receiver device to six from twelve.